Andrea LaPiana

President and Founder

Andrea started her career at Intersil as an applications engineer and has a wealth of hands on experience and knoweledge. She specializes in Cryptographic hardware design, logic synthesis, testing and verification.

Giuseppe LaPiana

Giuseppe started his career as an FPGA designer in a production environment and has over 12 years of ASIC design experience. He specializes in memory subsystem design, trusted architectures, physical implementation, STA and timing closure. He has developed design flows in 65nm, 45nm SOI, 32nm SOI, and 12nm process nodes with succesful tapeouts in each.